Method and apparatus for designing an emulation chip using a selectable fastpath topology
US7739094B1 · kind B1 · utility
6Cited by
1References
18Claims
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Key dates
| Filing date | Nov 22, 2006 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Aug 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for designing a processor-based emulation integrated circuit (chip) having a selectable fastpath topology. Included are initially designing an N-level fastpath topology comprising a plurality of processors, then reducing the N-level fastpath topology to an M-level topology such that the performance of the topology meets a design criterion, e.g., capable of evaluating data during a time of an emulation step. In this manner, an emulator chip designer may configure the fastpath topologies without redesigning the chip layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.