Packet processing switch and methods of operation thereof
US7739424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Oct 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.