Method and apparatus for stacked address, bus to memory data transfer
US7739451B1 · kind B1 · utility
27Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2002 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jan 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller (506) and Memory Controller (510) of Data Controller (500). Data is then transferred in response to the data pointers from BUFFER (512) and Buffer (514) and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.