Method and apparatus for rectifying errors in the presence of known trapping sets in iterative decoders and expedited bit error rate testing
US7739558B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2006 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jan 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/015
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associated with a programmable transmitter that is in communication with the device. The biased bits correspond to the variable nodes of the dominant trapping set. The method further includes transmitting random data from the programmable transmitter to the device, in which the random data includes one or more of the biased bits; measuring a number of error events corresponding to biased bits received by the device that cannot be decoded; and determining a true bit error rate of the device based on the measured number of error events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.