Synchronous to asynchronous logic conversion
US7739628B2 · kind B2 · utility
17Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2008 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Dec 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.