Integrated circuit having a clock tree
US7739641B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Sep 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a computer to generate a timing constraints file for controlling a clock tree synthesis tool, the method comprising: inputting into the computer data defining a circuit to be synthesised, the circuit including a plurality of timing paths each including at least one of a first timing portion, a second timing portion and a third timing portion; executing a tool in the computer to read the data and to analyse the delay on each the first and third portion of each the timing path, to compare the delays and to set a clock latency for at least one of start and end points of the second portion of at least one timing path in dependence on the comparison; and outputting a timing constraints file including commands for controlling the clock tree synthesis tool, the commands defining the clock latencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.