Semiconductor device
US7741724B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 1, 2008 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Oct 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention is directed to offer a semiconductor device having a structure capable of relaxing a mechanical stress applied to a bonding pad. A third interlayer insulation film having via holes is formed on a second interlayer insulation film to cover a third wiring layer. A third conductive layer is formed in the via hole. The third interlayer insulation film is composed of an array of a plurality of hexagonal column-shaped interlayer insulation films. And the via hole and the third conductive layer are formed to surround each hexagonal column-shaped interlayer insulation film. A fourth wiring layer connected with the third wiring layer through the third conductive layer is formed. The fourth wiring layer makes an uppermost wiring layer in an embodiment of this invention and serves as the bonding pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.