Providing running digital sum control in a precoded bit stream using precoder aware encoding
US7741980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2008 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Oct 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M5/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system includes a precoder-aware running digital sum (RDS) encoder that encodes user data as w-bit sub-blocks, to produce an encoded data block that meets block RDS constraints and consists of encoded data sub-blocks that meet sub-block RDS constraints. The sub-block constraints include the data sub-blocks having the same magnitude RDS before and after precoding. The encoder data block is further encoded using an error correction code to produce parity bits, and the parity bits are dispersed, as i-bit parity sub-blocks, between selected data sub-blocks to form a code word. The code word is then precoded to produce a precoded bit sequence for transmission over a channel. Sub-block run length limit (“RLL”) constraints may also be included, such that the encoded data block meets both RLL and RDS, with the encoded data sub-blocks meeting respective RLL and RDS sub-block constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.