Highly-scalable hardware-based traffic management within a network processor integrated circuit
US7742411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2007 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Aug 13, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A technique for managing traffic within a network processor integrated circuit (IC) involves establishing multiple queue groups, associating a different hardware counter with each queue group, and then using the hardware counters to support rate shaping and scheduling of all of the queues in the queue groups. For example, 512 queue groups of thirty-two queues each queue group are established for a total of 16,384 (16 k) different queues and a different hardware counter is associated with each queue group for a total of 512 hardware counters. The group-specific hardware counters are used to implement hardware-based rate shaping and scheduling of all 16 k queues in a resource efficient manner that supports high throughput, e.g., on the order of 40 Gbps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.