Method and system for phase and byte alignment on a multiplexed high speed bus
US7742507B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2006 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Oct 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and system for multiplexing a plurality of serialized data signals in which a first integrated circuit device generates a plurality of serialized data signals. A second integrated circuit device is in electrical communication with the first integrated circuit device. The second integrated circuit device includes a multiplexer operable to generate a multiplexed output signal from the plurality of serialized data signals received from the first integrated circuit. A phase data and byte snapshot back channel is transmitted from the second integrated circuit device to the first integrated circuit device. The phase data and byte snapshot back channel carries phase data and periodic snapshots of the serialized data signals. The phase data and byte snapshot back channel is used by the first integrated circuit device to adjust the phase of each of the plurality of serialized data signals to preserve bit and byte alignment. Such a method and system can be implemented as a 4×10 Gbit/Sec. system that is multiplexed to a 40 Gbit/Sec. stream as may be used in optical transmission systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.