On-chip shared memory based device architecture
US7743191B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2007 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Feb 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/415
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and architecture are provided for SOC (System on a Chip) devices for RAID processing, which is commonly referred as RAID-on-a-Chip (ROC). The architecture utilizes a shared memory structure as interconnect mechanism among hardware components, CPUs and software entities. The shared memory structure provides a common scratchpad buffer space for holding data that is processed by the various entities, provides interconnection for process/engine communications, and provides a queue for message passing using a common communication method that is agnostic to whether the engines are implemented in hardware or software. A plurality of hardware engines are supported as masters of the shared memory. The architectures provide superior throughput performance, flexibility in software/hardware co-design, scalability of both functionality and performance, and support a very simple abstracted parallel programming model for parallel processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.