Using SAM in error correcting code encoder and decoder implementations
US7743287B2 · kind B2 · utility
3Cited by
10References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2007 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Sep 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation to sequential accesses. According to the present invention, Forward Error Correcting Code encoder and decoder structures are shown to allow the use of SAM in their memory designs. Thus SAM is utilized in FECC implementations to achieve better area efficiency for the same amount of memory as well as higher throughput for the hardware implementations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.