Built-in at-speed bit error ratio tester
US7743288B1 · kind B1 · utility
14Cited by
13References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2005 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Jun 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.