Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit
US7743289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2007 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Dec 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first mathematical expression indicating a dependence of SER on an information storage node diffusion layer area at the same information storage node voltage Vn is derived with a use of a result of measuring a relationship between SER and the information storage node diffusion layer area of a storage circuit or an information holding circuit composed of MISFET using a plurality of information storage node voltages Vn as a parameter. Then, a second mathematical expression is derived from the measurement result by substituting a relationship indicating a dependence of SER on an information storage node voltage at the same information storage node diffusion layer area Sc into the first mathematical expression. SER can be calculated by substituting a desired information storage node diffusion layer area and a desired information storage node voltage of a storage circuit or an information holding circuit into the second mathematical expression.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.