Patent · US Active

Chip scale package fabrication methods

US7745261B2 · kind B2 · utility

7Cited by

3References

15Claims

0Family size

Assignee

Shanghai Kaihong Technology Co., Ltd. · CN

Inventors

Xiaochun Tan · Bellevue, US
Jun Guo · Tainan, TW

Key dates

Filing date	Apr 25, 2008
Grant date	Jun 29, 2010
Priority date	—
Expiry date	Jul 23, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/10156
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.