Method of fabricating micro-vertical structure
US7745308B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 2, 2009 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Apr 2, 2029 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0133
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a [111] crystal plane vertical to the second crystalline Si substrate, and etching an etched vertical surface of the second crystalline Si substrate using a crystalline wet etching process to improve the surface roughness and flatness of the etched vertical surface. As a result, no morphological defects occur on the etched vertical surface. Also, footings do not occur at an etch end-point due to the insulating layer pattern. In addition, the micro-vertical structure does not float in the air but is fixed to the first crystalline Si substrate, thereby facilitating subsequent processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.