Wiring structure of a semiconductor device, method of forming the wiring structure, non-volatile memory device including the wiring structure, and method of manufacturing the non-volatile memory device
US7745325B2 · kind B2 · utility
7Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2007 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Aug 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.