Reset signal filter
US7746131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2008 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reset signal filter includes a power voltage detector and a reset signal detector or includes only one reset signal detector. The power voltage detector includes a comparators and a basic logic gates (e.g. AND gate, OR gate, inverter, etc). The reset signal detector includes a comparator, N flip flops connected in series, an AND gate, an OR gate, a multiplexer and an output flip flop. The reset signal filter receives a first reset signal generated by a power voltage detector or a Schmitt trigger buffer and utilizes N flip flops to register the signal level of the first reset signal for N clock periods. Then the reset signal filter determines if the first rest signal is changed during N clock periods, and outputs a second reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.