Patent · US Active

NOR and NAND memory arrangement of resistive memory elements

US7746683B2 · kind B2 · utility

6Cited by

1References

6Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Kurt Hoffmann · Taufkirchen, DE
Christine Dehm · Koblenzer Straße, DE
Recai Sezi · Simmerath, DE
Andreas Walter · Egloffstein, DE

Key dates

Filing date	Apr 19, 2007
Grant date	Jun 29, 2010
Priority date	—
Expiry date	Apr 19, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG11C2213/79
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.