Time multiplexing logic in physical design domain for multiple instantiation
US7746785B2 · kind B2 · utility
1Cited by
5References
40Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2006 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Feb 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided to perform a time multiplexing logic in a module, are provided including identifying a driving flop and a receiving flop in the module, receiving a modified input signal, and identifying a worst case timing path for the modified input signal to transmit from the driving flop to the receiving flop. The time multiplexing logic of the apparatus and method further identifies a predetermined point of the worst case timing path, and inserts a logic unit at the predetermined point allowing the time multiplexing logic circuit to process and output the modified input signal at a maximum frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.