Decoding method and apparatus
US7746925B1 · kind B1 · utility
3Cited by
18References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Mar 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0349
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A feedback equalizer includes a summing unit having an output and first input for receiving a modulated signal, which includes a symbol defined by a first number of chips. A subsymbol processor is coupled to the output of the summing unit. The symbol processor is capable of generating a subsymbol waveform upon receipt of a second number of chips of the symbol. The second number is less than the first number. A feedback filter is coupled to a second input of the summing unit and the symbol processing unit to selectively filter the subsymbol waveform from the modulated signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.