Data recovery method, data recovery circuit, data transmitting/receiving apparatus and information processing apparatus
US7746971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2006 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Mar 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/068
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Serially transferred data is over sampled with a multiphase clock signal generated as a result of shifting a predetermined frequency clock signal by a predetermined phase each, to obtain over sampling data; generating clock patterns, having mutually different phase states according to a data phase state of the over sampling data. A first phase pattern generated from the over sampling data is compared with a second phase pattern generated from the clock pattern, and the number of bits to extract from the over sampling data is controlled. A phase error of the over sampling data is detected based on the first phase pattern and the second phase pattern. Bits to extract from the over sampling data is selected to restore the data based on the phase state of the clock pattern and the phase error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.