System and methods for performing deblocking in microprocessor-based video codec applications
US7747088B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2006 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Mar 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/86
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Two pairs of deblock instructions for performing deblock filtering on a horizontal row of pixels according to the H.264 (MPEG 4 part 10) and VC1 video codec algorithms. The first instruction of each pair has three 128-bit operands comprising the 16-bit components of a horizontal line of 8 pixels crossing a vertical block edge between pixels 4 and 5 in a YUV image, a series of filter threshold parameters, and a 128-bit destination operand for storing the output of the first instruction. The second instruction of each pair accepts the same 16-bit components as its first input, the output of the first instruction as its second input and a destination operand for storing an output of the second instruction as its third input. The instruction pairs are intended for use with the H.264 or VC1 video codecs respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.