Register access protocol in a multihreaded multi-core processor
US7747771B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Mar 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and mechanism for managing access to a plurality of registers in a processing device are contemplated. A processing device includes multiple nodes coupled to a ring bus, each of which include one or more registers which may be accessed by processes executing within the device. Also coupled to the ring bus is a ring control unit which is configured to initiate transactions targeted to nodes on the ring bus. Each of the nodes are configured receive and process bus transaction with a fixed latency whether or not the first transaction is targeted to the receiving node. The ring control unit is configured to periodically convey idle transactions on the ring bus in order to allow nodes responding to indeterminate transactions to gain access to the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.