Method and apparatus for early load retirement in a processor system
US7747841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2006 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Sep 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique known as checkpointed early load retirement, combines register checkpointing load-value prediction to manage long-latency loads. When a long-latency load reaches the retirement stage unresolved, the processor enters Clear mode by (1) taking a Checkpoint of the architectural registers, (2) supplying a load-value prediction to consumers, and (3) early-retiring the long-latency load. This unclogs retirement, thereby “clearing the way” for subsequent instructions to retire, and also allowing instructions dependent on the long-latency load to execute sooner. When the actual value returns from memory, it is compared against the prediction. A misprediction causes the processor to roll back to the checkpoint, discarding all subsequent computation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.