Dual ported replicated data cache
US7747896B1 · kind B1 · utility
3Cited by
8References
25Claims
0Family size
Inventors
Key dates
| Filing date | Jun 30, 2006 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Apr 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.