Synchronizing cross checked processors during initialization by miscompare
US7747902B2 · kind B2 · utility
0Cited by
7References
7Claims
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Key dates
| Filing date | Mar 13, 2008 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Jun 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.