Patent · US Active

Method for manufacturing an integrated circuit including an electrolyte material layer

US7749805B2 · kind B2 · utility

70Cited by
1References
26Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 10, 2005
Grant dateJul 6, 2010
Priority date
Expiry dateJul 21, 2028

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10N70/8833

Abstract

A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.