Method of manufacturing semiconductor device
US7749897B2 · kind B2 · utility
3Cited by
10References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Jul 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.