Field effect transistor and method of fabricating the same
US7750378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2006 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Apr 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.