Circuit for distributing a test signal applied to a pad of an electronic device
US7750656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2006 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Jun 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31723
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The circuit distributes a test signal applied to a pad of an electronic device that is enabled during test phases of the device and disabled during normal functioning. The circuit includes a “master” buffer, one or more “slave” buffers, one for each replicated pad, and an interconnection bus of the “master” and “slave” buffers. During a test phase, the “master” buffer replicates on the interconnection bus the test signal fed to a pad of the device, while the “slave” buffers convey to the various replica pads of the feed pad the signal present on the interconnection bus. During the normal operation of the device, the circuit remains disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.