Integrated circuit and testing circuit therein for testing and failure analysis
US7750658B2 · kind B2 · utility
2Cited by
5References
14Claims
0Family size
Inventor
Key dates
| Filing date | Jan 18, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Jul 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2831
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing circuit includes at least two contact terminals and a plurality of first resistors. The contact terminals are located on a substrate and respectively connected to two ends of an original circuit on the substrate. The first resistors are embedded in the substrate and respectively connected to a plurality of devices of the original circuit in parallel or in series.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.