Frequency measurement based frequency locked loop synthesizer
US7750685B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Jan 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first embodiment of the present invention relates to a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. A second embodiment of the present invention relates to a high resolution frequency measurement circuit that is capable of directly measuring the frequency of a high frequency signal to provide a high resolution frequency measurement using a lower frequency reference signal, and may include linear feedback shift register (LFSR) circuitry and LFSR-to-binary conversion circuitry. A third embodiment of the present invention relates to an FPLL having an FLL that includes the high resolution frequency measurement circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.