Circuits, architectures, apparatuses, systems, and methods for low voltage clock delay generation
US7750706B1 · kind B1 · utility
2Cited by
2References
25Claims
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Key dates
| Filing date | Jul 13, 2007 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Jan 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00097
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits, systems, and methods for generating a delayed clock signal. The circuit generally includes a first ramp generator configured to produce a first ramp signal in response to a reference clock signal, a first comparison circuit configured to compare the first ramp signal to a first threshold value in response to the reference clock signal to produce a comparison signal, a second ramp generator configured to produce a second ramp signal in response to the comparison signal, and a second comparison circuit configured to compare the second ramp signal to a second threshold value to produce the delayed clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.