Method and apparatus for biasing a floating node in an integrated circuit
US7750709B1 · kind B1 · utility
5Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2007 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Feb 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45542
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.