Calibration device and method thereof for pipelined analog-to-digital converter
US7750830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Nov 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A calibration device includes a comparison unit, a counting unit, a memory, and a compensation circuit. A residue of a sub analog-to-digital converter is compared with a first and a second voltage by the comparison unit for generating a comparison result. A number of times of the residue voltage, out of bounds defined by the first and the second voltage, is counted by the counting unit in an ith period according to the comparison result. The number of times of the residue voltage out of the bounds in an (i−1)th period is stored in the memory. A clock of the sub ADC is adjusted by the compensation circuit into a direction based on the number of times of the residue voltage out of the bounds in the ith period and the number of times of the residue voltage out of the bounds in the (i−1)th period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.