Electrostatic discharge protection circuit
US7751164B1 · kind B1 · utility
2Cited by
35References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | May 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing a parasitic capacitance of an electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) includes providing an ESD protection circuit including a plurality of transistors; coupling one end of a resistor to a shared drain of the plurality of transistors; and coupling an opposite end of the resistor to at least one of an input pad of the IC, a blocking capacitor of the IC and a transistor in the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.