Double data rate-single data rate input block and method for using same
US7751275B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Apr 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a double data rate (DDR) input block comprising first and second input registers corresponding to a DDR input of the DDR input block. The first and second input registers are coupled to the DDR input. The DDR input block is configured to load a first data into the first input register and a second data into the second input register during a single clock cycle of a system clock, thereby operating at double data input during a single clock cycle. A single data rate/double data rate (SDR/DDR) input block may be operated in either SDR or DDR mode. The DDR input block may he used with a scannable output reduction block. The DDR input block may be used in systems utilizing a content addressable memory (CAM) or a random access memory (RAM), or other types of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.