Design structure for forwarding store data to loads in a pipelined processor
US7752393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | May 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding store data to loads in a pipelined processor is provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.