Scheduler design to optimize system performance using configurable acceleration engines
US7752592B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 2007 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reusable hardware control structure is provided for a hardware acceleration engine that can be configured for implementation within an electronic integrated circuit design according to any one of a plurality of configuration alternatives. The reusable hardware control structure comprises a digital logic circuit design developed to receive configuration data from the hardware acceleration engine describing a selected configuration alternative. The selected configuration alternative is any one of the plurality of configuration alternatives. The digital logic circuit design is developed to process the configuration data to provide an evaluation of an input-to-output latency and an input blocking pattern of the hardware acceleration engine configured according to the selected configuration alternative. The evaluation is capable of being leveraged by control logic within the electronic integrated circuit design to increase utilization of the hardware acceleration engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.