Micro discharge (MD) plasma display panel including electrode layer directly laminated between upper and lower subtrates
US7755290B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2006 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | May 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2211/265
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A Plasma Display Panel (PDP) includes a dielectric layer having a plurality of dielectric-layer perforated holes arranged in a matrix; and upper and lower electrode layers having electrode-layer perforated holes connected to the dielectric-layer perforated holes and arranged on both surfaces of the dielectric layer; the upper electrode layer includes a plurality of first electrodes extending in a first direction, the plurality of first electrodes surrounding a group of electrode-layer perforated holes arranged in the first direction; and the lower electrode layer includes a plurality of second electrodes extending in a second direction different from the first direction, the plurality of second electrodes surrounding a group of electrode-layer perforated holes arranged in the second direction. Individual electrodes surrounding the electrode-layer perforated holes protrude from the dielectric layer toward the centers of the perforated holes such that a facing discharge is generated between the upper and lower individual electrodes, resulting in a PDP having stable characteristics and high efficiency and having a simple structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.