Circuit combining level shift function with gated reset
US7755394B2 · kind B2 · utility
2Cited by
2References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2008 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Aug 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.