Differential impedance matching circuit and method with harmonic suppression
US7755448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2008 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Jan 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Matching network circuits and a method are shown for suppressing a harmonic frequency in a matching network. The circuits and method involve impedance matching first and second differential input nodes to a single ended output node using a first reactive impedance selected to pass a resonant frequency. They also involve suppressing a harmonic frequency of a common mode signal presented at the first and second differential input nodes by providing a series resonance from the first and second differential input nodes to a radio frequency ground potential, where the series resonance is selected to pass the harmonic frequency to the radio frequency ground potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.