Power-rail ESD protection circuit with ultra low gate leakage
US7755871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2007 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Jan 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.