Memory including a performance test circuit
US7755960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2008 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Mar 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.