Built in self test (BIST) for high-speed serial transceivers
US7756197B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2004 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Mar 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03038
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A relatively high-speed serial data transmitter incorporates built in self test (BIST). The BIST circuit advantageously provides tests modes to obviate the need to build expensive test equipment for high-speed serial data devices, such as a serializer/deserializer (SerDes) or other transceivers. Multiple data paths in a finite impulse response (FIR) filter of transmitter of the SerDes or a transceiver can be independently tested. The transmitter output can also be selectively degraded to test a receiver of a transceiver. An attenuated output signal can be provided to test receiver sensitivity. A low-pass filter can be invoked to emulate a backplane, while a loopback circuit can provide the emulated backplane attenuation to the receiver to permit testing of the equalization circuitry of a receiver without requiring the presence of an actual backplane for testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.