Multi-bit memory device and memory system
US7757153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2006 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | May 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device, memory system and read method are disclosed. The memory device comprises a memory cell array comprising a plurality of memory blocks each having a plurality of memory cells adapted to store N bits, where N is an integer greater than 1, a page buffer configured to perform a read operation adapted to read data from the memory cell array and output read data, an error correction circuit configured to detect and correct an error in read data stored in a memory block K and generate corresponding error information, and a control circuit configured to reduce the number of bits stored in the plurality of memory cells for memory block K from N to J, where J is an integer less than N but greater than zero, in response to the error information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.