Method and system to construct a data-flow analyzer for a bytecode verifier
US7757223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2005 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Mar 9, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.