Patent · US Active

Dummy active area implementation

US7759182B2 · kind B2 · utility

2Cited by
5References
16Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 8, 2006
Grant dateJul 20, 2010
Priority date
Expiry dateJun 28, 2028

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D89/10

Abstract

Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.