Dual structure FinFET and method of manufacturing the same
US7759737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Jan 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6213
Abstract
Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field oxide layer, and raised source and drain can be implemented to reduce serial resistance components of the source and drain to increase current drivability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.